/* Using the indirect addressing mode instruction st
 * clear registers  r0 to r15
 * Hint: SRAM address 0x0000 to 0x0001F map to registers r0 to r31 
 */

.INCLUDE <m328pdef.inc>
Setup:
    rcall PreReg0_20
	rcall Clr0_15
	rjmp  Setup

Clr0_15:
    clr  XH      ; r27
	clr  XL      ; r26
	clr  r25
    ldi  r24,16  ; clear registers r0 to r15 
clr_loop:  
    st   X+,r25
	dec  r24
	brne clr_loop
	ret

PreReg0_20:
    clr  XH      ; r27
	clr  XL      ; r26
    ldi  r24,21  ; clear registers r0 to r20
reg_loop:  
    st   X+,r24
	dec  r24
	brne reg_loop
	ret